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CY2DL1504
1:4 Differential LVDS Fanout Buffer with Selectable Clock Input
Features
Functional Description
The CY2DL1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DL1504 can select between LVPECL or LVDS input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The output enable function allows the outputs to be asynchronously driven to a high-impedance state. The device has a fully differential internal architecture that is optimized to achieve low-additive jitter and low-skew at operating frequencies of up to 1.5 GHz.
Select between low-voltage positive emitter-coupled logic (LVPECL) or low-voltage differential signal (LVDS) input pairs to distribute to four LVDS output pairs 30-ps maximum output-to-output skew 480-ps maximum propagation delay 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) Up to 1.5-GHz operation Output enable and synchronous clock enable functions 20-pin thin shrunk small outline package (TSSOP) 2.5-V or 3.3-V operating voltage[1] Commercial and industrial operating temperature range

Logic Block Diagram
VDD VSS Q0 Q0# IN0 IN0# IN1 IN1# Q2 Q2# IN_SEL
100k VDD 100k
Q1 Q1#
Q D
Q3 Q3#
CLK_EN
VDD 100k
OE
Note 1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation Document Number: 001-56312 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 25, 2011
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Contents
Pinout ................................................................................ 3 Absolute Maximum Ratings ............................................ 4 Operating Conditions....................................................... 4 DC Electrical Specifications ............................................ 5 AC Electrical Specifications ............................................ 6 Ordering Information...................................................... 10 Ordering Code Definition........................................... 10 Package Diagram............................................................ 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15
Document Number: 001-56312 Rev. *E
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Pinout
Figure 1. Pin Diagram - CY2DL1504 20-Pin TSSOP Package
VSS CLK_EN IN_SEL IN0 IN0# IN1 IN1# OE VSS VDD
1 2 3 4 5 6 7 8 9 10
20 19 18
Q0 Q0# VDD Q1 Q1# Q2 Q2# VSS Q3 Q3#
CY2DL1504
17 16 15 14 13 12 11
Table 1. Pin Definitions Pin No. 1,9,13 2 Pin Name VSS CLK_EN Input Pin Type Power Ground Synchronous clock enable. Low-voltage complementary metal oxide semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL); When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are held high Input clock select pin. LVCMOS/LVTTL; When IN_SEL = Low, the IN0/IN0# differential input pair is active When IN_SEL = High, the IN1/IN1# differential input pair is active LVDS input clock. Active when IN_SEL = Low LVDS complementary input clock. Active when IN_SEL = Low LVPECL input clock. Active when IN_SEL = High LVPECL complementary input clock. Active when IN_SEL = High Output enable. LVCMOS/LVTTL; When OE = Low, Q(0:3) and Q(0:3)# outputs are disabled (see IOZ) Power supply LVDS complementary output clocks LVDS output clocks Description
3
IN_SEL
Input
4 5 6 7 8 10,18 11,14,16,19 12,15,17,20
IN0 IN0# IN1 IN1# OE VDD Q(0:3)# Q(0:3)
Input Input Input Input Input Power Output Output
Document Number: 001-56312 Rev. *E
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CY2DL1504
Absolute Maximum Ratings
Parameter VDD VIN[2] VOUT[2] TS ESDHBM LU UL-94 MSL Supply voltage Input voltage, relative to VSS DC output or I/O voltage, relative to VSS Storage temperature Electrostatic discharge (ESD) protection (Human body model) Latch up Flammability rating Moisture sensitivity level At 1/8 in. Description Condition Nonfunctional Nonfunctional Nonfunctional Nonfunctional JEDEC STD 22-A114-B Min -0.5 -0.5 -0.5 -55 2000 Max 4.6 lesser of 4.0 or VDD + 0.4 lesser of 4.0 or VDD + 0.4 150 - Unit V V V C V
Meets or exceeds JEDEC Spec JESD78B IC Latchup Test V-0 3
Operating Conditions
Parameter VDD TA tPU Supply voltage Ambient operating temperature Power ramp time Description Condition 2.5-V supply 3.3-V supply Commercial Industrial Power-up time for VDD to reach minimum specified voltage. (Power ramp must be monotonic) Min 2.375 3.135 0 -40 0.05 Max 2.625 3.465 70 85 500 Unit V V C C ms
Note 2. The voltage on any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
Document Number: 001-56312 Rev. *E
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DC Electrical Specifications
(VDD = 3.3 V 5% or 2.5 V 5%; TA = 0 C to 70 C (Commercial) or -40 C to 85 C (Industrial)) Parameter IDD VIH1 Description Operating supply current Input high voltage, LVDS and LVPECL input clocks, IN0, IN0#, IN1, and IN1# Input low voltage, LVDS and LVPECL input clocks, IN0, IN0#, IN1, and IN1# Input high voltage, CLK_EN, IN_SEL, and OE Input low voltage, CLK_EN, IN_SEL, and OE Input high voltage, CLK_EN, IN_SEL, and OE Input low voltage, CLK_EN, IN_SEL, and OE LVDS input differential amplitude LVPECL input differential amplitude Input common mode voltage Input high current, All inputs Input low current, All inputs VDD = 3.3 V VDD = 3.3 V VDD = 2.5 V VDD = 2.5 V See Figure 3 on page 7 See Figure 3 on page 7 See Figure 3 on page 7 Input = Input = VDD[6] VSS[6] Condition All LVDS outputs terminated with a load of 100 [3, 4] Min - - Max 61 VDD + 0.3 Unit mA V
VIL1
-0.3
-
V
VIH2 VIL2 VIH3 VIL3 VID_LVDS[5] VID_LVPECL[5] VICM IIH IIL VPP VOCM VOCM IOZ RP
2.0 -0.3 1.7 -0.3 0.4 0.4 0.5 - -150 250 1.125 - -15 60
VDD + 0.3 0.8 VDD + 0.3 0.7 0.8 1.0 VDD - 0.2 150 - 470 1.375 50 15 140
V V V V V V V A A mV V mV A k
LVDS differential output voltage peak VDD = 3.3 V or 2.5 V, to Peak, Single-ended RTERM = 100 between Q and Q# pairs[3, 7] LVDS differential output common VDD = 3.3 V or 2.5 V, mode voltage RTERM = 100 between Q and Q# pairs[3, 7] Change in VOCM between complementary output states Output leakage current VDD = 3.3 V or 2.5 V, RTERM = 100 between Q and Q# pairs[3, 7] OE = VSS, VOUT = 0.75V - 1.75V
Internal pull-up/pull-down resistance, CLK_EN has pull-up only LVCMOS logic inputs IN_SEL has pull-down only OE has pull-up only Input capacitance Measured at 10 MHz; per pin
CIN
-
3
pF
Notes 3. Refer to Figure 2 on page 7. 4. IDD includes current that is dissipated externally in the output termination resistors. 5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV. 6. Positive current flows into the input pin, negative current flows out of the input pin. 7. Refer to Figure 4 on page 7.
Document Number: 001-56312 Rev. *E
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AC Electrical Specifications
(VDD = 3.3 V 5% or 2.5 V 5%; TA = 0 C to 70 C (Commercial) or -40 C to 85 C (Industrial)) Parameter FIN FOUT tPD[8] tODC[9] tSK1[10] tSK1 D[10] Description Input frequency Output frequency Propagation delay input pair to output pair Output duty cycle Output-to-output skew Device-to-device output skew Condition FOUT = FIN Input rise/fall time < 1.5 ns (20% to 80%) Diff input at 50% duty cycle Frequency range up to 1 GHz Any output to any output, with same load conditions at DUT Any output to any output between two or more devices. Devices must have the same input and have the same output load. Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz 156.25 MHz, 12 kHz to 20 MHz offset; input rise/fall time < 150 ps (20% to 80%), VID > 400 mV 50% duty cycle at input, 20% to 80% of full swing (VOL to VOH) Input rise/fall time < 1.5 ns (20% to 80%) Measured at 1 GHz. Synchronous clock enable (CLK_EN) switched low Synchronous clock enable (CLK_EN) switched high Min DC DC - 48 - - Typ - - - - - - Max 1.5 1.5 480 52 30 150 Unit GHz GHz ps % ps ps
PNADD
Additive RMS phase noise 156.25 MHz Input Rise/fall time < 150 ps (20% to 80%) VID > 400 mV
tJIT[11]
Additive RMS phase jitter (Random)
- - - - - - -
- - - - - - -
-120 -135 -135 -150 -154 -155 0.11
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps
tR, tF[12]
Output rise/fall time, single-ended
-
-
300
ps
tSOD tSOE
Time from clock edge to outputs disabled Time from clock edge to outputs enabled
- -
- -
700 700
ps ps
Notes 8. Refer to Figure 5 on page 7. 9. Refer to Figure 6 on page 7. 10. Refer to Figure 7 on page 8. 11. Refer to Figure 8 on page 8. 12. Refer to Figure 9 on page 8.
Document Number: 001-56312 Rev. *E
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CY2DL1504
Figure 2. LVDS Output Termination
Z=50
Q BUF
100 Z=50
Q#
Figure 3. Input Differential and Common Mode Voltages
IN VID IN#
VA VICM = (VA + VB)/2 VB
Figure 4. Output Differential and Common Mode Voltages
Q VPP Q#
VA
VOCM = (VA + VB)/2 VOCM = | VOCM1 - VOCM2 |
VB
Figure 5. Input to Any Output Pair Propagation Delay
IN IN # QX Q X#
t PD
Figure 6. Output Duty Cycle
QX Q X#
tPW tPERIOD t tODC = PW tPERIOD
Document Number: 001-56312 Rev. *E
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Figure 7. Output-to-output and Device-to-device Skew
QX QX# Device 1 QY Q Y# tSK1 QZ Device 2 QZ# tSK1 D
Figure 8. RMS Phase Jitter
Phase noise
Noise Power Phase noise mark
Offset Frequency f1 f2 Area Under the Masked Phase Noise Plot
RMS Jitter
Figure 9. Output Rise/Fall Time
QX 20% QX #
80% 80% 20% tR tF VPP
Document Number: 001-56312 Rev. *E
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CY2DL1504
Figure 10. Synchronous Clock Enable Timing
CLK_EN IN IN#
tSOD tPD tSOE
QX QX#
Document Number: 001-56312 Rev. *E
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CY2DL1504
Ordering Information
Part Number Pb-free CY2DL1504ZXC CY2DL1504ZXCT CY2DL1504ZXI CY2DL1504ZXIT 20-Pin TSSOP 20-Pin TSSOP 20-Pin TSSOP 20-Pin TSSOP Commercial, 0 C to 70 C Commercial, 0 C to 70 C Industrial, -40 C to 85 C Industrial, -40 C to 85 C Type Production Flow
Ordering Code Definition
CY 2DL15 04 ZX C/I T
Tape and reel Temperature range C = Commercial I = Industrial Pb-free TSSOP package Number of differential output pairs Base part number Company ID: CY = Cypress
Document Number: 001-56312 Rev. *E
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CY2DL1504
Package Diagram
Figure 11. 20-Pin Thin Shrunk Small Outline Package (4.40 mm Body) ZZ20
51-85118 *C
Document Number: 001-56312 Rev. *E
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Acronyms
Table 2. Acronyms Used in this Document Acronym ESD HBM JEDEC LVDS LVCMOS LVPECL LVTTL OE RMS TSSOP Description Electrostatic discharge Human body model Joint electron devices engineering council Low-voltage differential signal Low-voltage complementary metal oxide semiconductor Low-voltage positive emitter-coupled logic Low-voltage transistor-transistor logic Output enable Root mean square Thin shrunk small outline package
Document Conventions
Table 3. Units of Measure Symbol C dBc GHz Hz k A F s mA ms mV MHz ns pF ps V W degree Celsius decibels relative to the carrier giga hertz hertz kilo ohm micro amperes micro Farad micro second milliamperes millisecond millivolt megahertz nano second ohm pico Farad pico second volts watts Unit of Measure
Document Number: 001-56312 Rev. *E
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Document History Page
Document Title: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Document Number: 001-56312 Revision ** *A ECN 2782891 2838613 Orig. of Change CXQ CXQ Submission Date 10/09/09 New Datasheet. Description of Change
01/05/2010 Changed status from "ADVANCE" to "PRELIMINARY". Changed from 0.34 ps to 0.25 ps maximum additive jitter in "Features" on page 1 and in tJIT in the AC Electrical Specs table on page 5. Added tPU spec to the Operating Conditions table on page 3. Changed max IDD spec in the DC Electrical Specs table on page 4 from 60 mA to 61 mA. Removed VOD and VOD specs from the DC Electrical Specs table on page 4. Changed IOZ in the DC Electrical Specs table on page 4 from min of -10 uA to -15 uA and from max of 10 uA to 15 uA. Added RP spec in the DC Electrical Specs table on page 4. Min = 60 k, Max = 140 k. Added a measurement definition for CIN in the DC Electrical Specs table on page 4. Added VPP and VPP specs to the AC Electrical Specs table on page 5. VPP min = 250 mV and max = 470 mV; VPP max = 50 mV. Changed letter case and some names of all the timing parameters in the AC Electrical Specs table on page 5 to be consistent with EROS. Lowered all additive phase noise mask specs by 3 dB in the AC Electrical Specs table on page 5. Added condition to tR and tF specs in the AC Electrical specs table on page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%). Changed letter case and some names of all the timing parameters in Figures 4, 5, 6, 7 and 9, to be consistent with EROS. Updated Figure 4 with definition for VPP and VPP. 08/18/2010 Changed from 0.25 ps to 0.11 ps maximum additive jitter in "Features" on page 1 and in tJIT in the AC Electrical Specs table on page 5. Added "Functional equivalent to ICS8543i" to the "Features" section. Changed pin 13 in Figure 1 and Table 1 from VDD to VSS. Changed pin 8 description in Table 1 from "high impedance" to "disabled". Added note 6 to describe IIH and IIL specs. Removed reference to data distribution from "Functional Description". Changed RP for diff inputs from 100 k to 150 k in the Logic Block Diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the DC Electrical Specs table. Split VID into separate specs in DC Electrical Specs table: 0.4 V min and 0.8 V max for LVDS, 0.4 V min and 1.0 V max for LVPECL. Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs table. Added "Frequency range up to 1 GHz" condition to tODC spec. Changed tOD in the AC Electrical Specs table from 3 ns max to 5 ns max. Added Acronyms and Ordering Code Definition.
*B
3010332
CXQ
Document Number: 001-56312 Rev. *E
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Document Title: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Document Number: 001-56312 Revision *C ECN 3090644 Orig. of Change CXQ Submission Date 11/19/2010 Description of Change Changed VIN and VOUT specs from 4.0V to "lesser of 4.0 or VDD + 0.4" Removed 200mA min LU spec, replaced with "Meets or exceeds JEDEC Spec JESD78B IC Latchup Test" Added "VOUT = 0.75V - 1.75V" to IOZ comments. Moved VPP from AC spec table to DC spec table, removed VPP. Removed RP spec for differential input clock pins INX and INX#. Changed CIN condition to "Measured at 10 MHz". Changed PNADD specs for 10kHz, 10MHz, and 20MHz offsets. Added "Measured at 1 GHz" to tR, tF spec condition. Removed specs tS, tH, tOD, and tOE from AC spec table. Removed VPP reference from Figure 4. Removed "Preliminary" status heading. Removed "Functional equivalent" bullet on page 1. Added "(see IOZ)" note to pin 8 description in Pin Definitions. Fixed typo and removed resistors from INX/INX# in Logic Block Diagram. Added Figure 10 to describe TSOE and TSOD. Post to external web.
*D
3135189
CXQ
01/12/2011
*E
3090938
CXQ
02/25/11
Document Number: 001-56312 Rev. *E
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(c) Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-56312 Rev. *E
Revised February 25, 2011
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